Fabrication, Characterization and Integration of Resistive Random Access Memories

The functionalities and performances of today's computing systems are increasingly dependent on the memory block. This phenomenon, also referred as the Von Neumann bottleneck, is the main motivation for the research on memory technologies. Despite CMOS technology has been improved in the last 50 years by continually increasing the device density, today's mainstream memories, such as SRAM, DRAM and Flash, are facing fundamental limitations to continue this trend. These memory technologies, based on charge storage mechanisms, are suffering from the easy loss of the stored state for devices scaled below 10 nm. This results in a degradation of the performance, reliability and noise margin. The main motivation for the development of emerging non volatile memories is the study of a different mechanism to store the digital state in order to overcome this challenge. Among these emerging technologies, one of the strongest candidate is Resistive Random Access Memory (ReRAM), which relies on the formation or rupture of a conductive filament inside a dielectric layer. This thesis focuses on the fabrication, characterization and integration of ReRAM devices. The main subject is the qualitative and quantitative description of the main factors that influence the resistive memory electrical behavior. Such factors can be related either to the memory fabrication or to the test environment. The first category includes variations in the fabrication process steps, in the device geometry or composition. We discuss the effect of each variation, and we use the obtained database to gather insights on the ReRAM working mechanism and the adopted methodology by using statistical methods. The second category describes how differences in the electrical stimuli sent to the device change the memory performances. We show how these factors can influence the memory resistance states, and we propose an empirical model to describe such changes. We also discuss how it is possible to control the resistance states by modulating the number of input pulses applied to the device. In the second part of this work, we present the integration of the fabricated devices in a CMOS technology environment. We discuss a Verilog-A model used to simulate the device characteristics, and we show two solutions to limit the sneak-path currents for ReRAM crossbars: a dedicated read circuit and the development of selector devices. We describe the selector fabrication, as well as the electrical characterization and the combination with our ReRAMs in a 1S1R configuration. Finally, we show two methods to integrate ReRAM devices in the BEoL of CMOS chips

Heterogeneous integration of ReRAM crossbars in a CMOS foundry chip

In this paper, we present a heterogeneous integration of ReRAMs with standard CMOS technology by post-processing the Back-End-of-the-Line (BEOL) of fully finished CMOS chips

A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs (invited)

Field Programmable Gate Arrays (FPGAs) rely heavily on complex routing architectures. The routing structures use programmable switches and account for a significant share in the total area, delay and power consumption numbers. With the ability of being monolithically integrated with CMOS chips, Resistive Random Access Memories (RRAMs) enable high-performance routing architectures through the replacement of Static Random Access Memory (SRAM)-based programming switches. Exploiting the very low on-resistance state achievable by RRAMs as well as the improved tolerance to power supply reduction, RRAM-based routing multiplexers can be used to significantly reduce the power consumption of FPGA systems with no performance compromises. By evaluating the opportunities of ultra-low-power RRAM-based FPGAs at the system level, we see an improvement of 12%, 26% and 81% in area, delay and power consumption at a mature technology node

Pragmatic OxRAM compact model ready to use for design studies

International audienceWe propose a pragmatic OxRAM device compact model describing SET, RESET, read operations and accounting for variability. The model is implemented in Verilog-A and usable with standard SPICE simulator. The objective is not to provide physical insights into OxRAM device operation but to develop a robust model, simple to calibrate and accounting for the main effect for design studies. It includes the dependency of Low Resistive State (LRS) resistance with compliance current, and of High Resistive State (HRS) resistance with the programming voltage: the proposed model is able to describe multi-level OxRAM. Switching time variation with programming voltages for SET and RESET operations is also included. It is validated on HFO2 OxRAM device through the measurements of isolated 1T-1R structure and 16kb matrix

Evolution of oxygen vacancies under electrical characterization for HfOx-based ReRAMs

Recently, studies on ReRAMs and their reliability have received increased attention. The reliability issue is due to the nature of oxygen vacancies behaviour under biasing conditions which necessitate further studies to achieve an in-depth understanding. In this work, we fabricated several HfOx ReRAM devices with different structure, material, and thickness, followed by a study of their electrical characteristics under DC biasing. We show an improvement in the switching parameters through engineering of the device structure. Moreover, we demonstrate a certain required thickness for the oxide layer for the ease of oxygen vacancies relocations, thinner oxide layer led to the common ReRAMs performance failure in the low resistance state

The key impact of incorporated Al2O3 barrier layer on W-based ReRAM switching performance

In this article, we inspected the bipolar resistive switching behavior of W-based ReRAMs, using HfO2 as switching layer. We have shown that the switching properties can be significantly enhanced by incorporating an Al2O3 layer as a barrier layer. It stabilizes the resistance states and lowers the operating current. Al2O3 acts as an oxygen scavenging blocking layer at W sides, results in the filament path constriction at the Al2O3/HfO2 interface. This leads to the more controllable reset operation and consecutively the HRS properties improvement. This allows the W/Al2O3/HfO2/Pt to switch at 10 times lower operating current of 100 mu A and 2 times higher memory window compared to the W/HfO2/Pt stacks. The LRS conduction of devices with the barrier layer is in perfect agreement with the Poole-Frenkel model

The key impact of incorporated Al2O3barrier layer on W-based ReRAM switching performance

In this article, we inspected the bipolar resistive switching behavior of W-based ReRAMs, using HfO2 as switching layer. We have shown that the switching properties can be significantly enhanced by incorporating an Al2O3 layer as a barrier layer. It stabilizes the resistance states and lowers the operating current. Al2O3 acts as an oxygen scavenging blocking layer at W sides, results in the filament path constriction at the Al2O3/HfO2 interface. This leads to the more controllable reset operation and consecutively the HRS properties improvement. This allows the W/Al2O3/HfO2/Pt to switch at 10 times lower operating current of 100 μA and 2 times higher memory window compared to the W/HfO2/Pt stacks. The LRS conduction of devices with the barrier layer is in perfect agreement with the Poole-Frenkel model

Effect of metal buffer layer and thermal annealing on HfOx-based ReRAMs

In this paper, we investigate different methods and approaches in order to improve the electrical characteristics of Pt/HfOx/TiN ReRAM devices. We discuss the improvement of the ReRAM electrical characteristics after the insertion of a Hf and Ti buffer layer. As a result, the resistance window increases more that 10 times, and the set and reset voltages decrease both in absolute value and variability. Furthermore, we show the influence of an annealing step at different temperatures on the Pt/HfOx/Hf/TiN memory devices on forming voltage and HRS. Considering the importance of achieving high density memory, we demonstrated the possibility of multi-level resistance state in the fabricated devices bu controlling the enforced compliance current. In addition, we show the endurance characteristic of the fabricated memories and their error rate. Finally, we report the transient behavior of the memory devices, investigating the device speed and switching mechanism

Effect of Hf Metal Layer on the Switching Characteristic of HfOX-based Resistive Random Access Memory

In this study, we propose the insertion of an ultrathin Hf layer at the interface between TiN (top electrode) and HfOX (electrolyte), and then studied its effect on the device electrical properties. In order to obtain the desired switching characteristics, the Hf layer thickness must be precisely engineered. The device with optimized Hf layer thickness exhibits better uniformity and lower forming voltage. This could be explained by the role of Hf layer in the creation of permanent oxygen vacancies in the oxide layer, which facilitates the switching phenomena

Cognitive Computing with Non-Volatile Memory Elements

Cognitive Computing with Non-Volatile Memory Element